tm june 2007 fdb12n50 / fdi12n 50 n-channel mosfet ?2007 fairchild semiconductor corporation fdb12n50tm re v . a1 www.fairchildsemi.com 1 unifet tm fdb12n50tm n-channel mosfet 500v, 11.5a, 0.65 features ?r ds(on) = 0.55 ( typ.)@ v gs = 10v, i d = 6a ? low gate charge ( typ. 22nc) ? low c rss ( typ. 12pf) ? fast switching ? 100% avalanche tested ? improved dv/dt capability ? rohs compliant description these n-channel enhancement mode power field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has be en especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficient switched mode power s upplies and active power factor correction. d g s d 2 -pak fdb series g s % i 2 -pak fdi series gs d mosfet maximum ratings t c = 25 o c unless otherwise noted thermal characteristics symbol parameter ratings units v dss drain to source voltage 500 v v gss gate to source voltage 30 v i d drain current -continuous (t c = 25 o c) 11.5 a -continuous (t c = 100 o c) 6.9 i dm d r a i n c u r r e n t - p u l s e d (note 1) 46 a e as single pulsed avalanche energy (note 2) 456 mj i ar avalanche current (note 1) 11.5 a e ar repetitive avalanche energy (note 1) 16.7 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t c = 25 o c) 165 w - derate above 25 o c1.33w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering purpose, 1/8? from case for 5 seconds 300 o c symbol parameter ratings units r jc thermal resistance, junction to case 0.75 o c/w r ja * thermal resistance, junction to ambient* 40 r ja thermal resistance, junction to ambient 62.5 *when mounted on the minimum pad size recommended (pcb mount)
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50 tm rev. a1 www.fairchildsemi.com 2 package marking and ordering information t c = 25 o c unless otherwise noted electrical characteristics off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity fdb12n50 fdb12n50tm d 2 -pak 330mm 24mm 800 fdi12n50 FDI12N50TU i 2 -pak - - 50 symbol parameter test conditions min. typ. max. units bv dss drain to source breakdown voltage i d = 250 p a, v gs = 0v, t j = 25 o c 500 - - v ' bv dss / ' t j breakdown voltage temperature coefficient i d = 250 p a, referenced to 25 o c - 0.66 - v/ o c i dss zero gate voltage drain current v ds = 500v, v gs = 0v - - 1 p a v ds = 400v, t c = 125 o c--10 i gss gate to body leakage current v gs = 30v, v ds = 0v - -
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50tm rev. a1 www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 46810 0.1 1 10 40 -55 o c 150 o c *notes: 1. v ds = 20v 2. 250 p s pulse test 25 o c i d ,drain current[a] v gs ,gate-source voltage[v] 110 1 10 20 *notes: 1. 250 p s pulse test 2. t c = 25 o c v gs = 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v i d ,drain current[a] v ds ,drain-source voltage[v] 30 0 5 10 15 20 25 0.4 0.6 0.8 1.0 1.2 1.4 *note: t j = 25 o c v gs = 20v v gs = 10v r ds(on) [ : ] , drain-source on-resistance i d , drain current [a] 0.3 0.6 0.9 1.2 1.5 1.8 1 10 100 *notes: 1. v gs = 0v 2. 250 p s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0.1 1 10 0 500 1000 1500 2000 c oss c iss c iss = c gs + c gd ( c ds = shorted ) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 30 0 5 10 15 20 25 0 2 4 6 8 10 *note: i d = 11.5a v ds = 100v v ds = 250v v ds = 400v v gs , gate-source voltage [v] q g , total gate charge [nc]
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50tm rev. a1 www.fairchildsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature figure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 11. transient thermal response curve -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 *notes: 1. v gs = 0v 2. i d = 250 p a bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c ] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 *notes: 1. v gs = 10v 2. i d = 6a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature [ o c ] 25 50 75 100 125 150 0 2 4 6 8 10 12 14 i d , drain current [a] t c , case temperature [ o c ] 110100 0.01 0.1 1 10 100 20 p s 100 p s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse 800 dc 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 1e-3 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 *notes: 1. z t jc (t) = 0.75 o c/w max. 2. duty factor, d=t 1 /t 2 3. t jm - t c = p dm * z t jc (t) 0.5 single pulse thermal response [ z t jc ] rectangular pulse duration [sec] 5 t 1 p dm t 2
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50 tm rev. a1 www.fairchildsemi.com 5 gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50 / fdi12n50 rev. a www.fairchildsemi.com 6 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g sam e type as d u t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( d riv e r ) i sd ( d u t ) v ds ( dut ) v dd b ody d iode forw ard v oltage d rop v sd i fm , b ody d iode forw ard c urrent b ody d iode r everse c urrent i rm b ody d iode r ecovery dv/dt di/dt d = g ate p ulse w idth g ate pulse period -------------------------- dut v ds + _ driver r g sam e type as d u t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( d riv e r ) i sd ( d u t ) v ds ( dut ) v dd b ody d iode forw ard v oltage d rop v sd i fm , b ody d iode forw ard c urrent b ody d iode r everse c urrent i rm b ody d iode r ecovery dv/dt di/dt d = g ate p ulse w idth g ate pulse period -------------------------- d = g ate p ulse w idth g ate pulse period --------------------------
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50tm rev. a1 www.fairchildsemi.com 7 mechanical dimensions 10.00 0.20 10.00 0.20 (8.00) (4.40) 1.27 0.10 0.80 0.10 0.80 0.10 (2xr0.45) 9.90 0.20 4.50 0.20 0.10 0.15 2.40 0.20 2.54 0.30 15.30 0.30 9.20 0.20 4.90 0.20 1.40 0.20 2.00 0.10 (0.75) (1.75) (7.20) 0 ~3 1.20 0.20 9.20 0.20 15.30 0.30 4.90 0.20 (0.40) 2.54 typ 2.54 typ 1.30 +0.10 ?0.05 0.50 +0.10 ?0.05 d 2 -pak
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50tm rev. a1 www.fairchildsemi.com 8 mechanical dimensions i 2 -pak 9.90 r 0.20 2.40 r 0.20 4.50 r 0.20 1.27 r 0.10 1.47 r 0.10 (45 q ) 0.80 r 0.10 10.00 r 0.20 2.54 typ 2.54 typ 13.08 r 0.20 9.20 r 0.20 1.20 r 0.20 10.08 r 0.20 max13.40 max 3.00 (0.40) (1.46) (0.94) 1.30 +0.10 ?0.05 0.50 +0.10 ?0.05
fdb12n50 / fdi12n 50 n-channel mosfet fdb12n50 tm rev. a1 www.fairchildsemi.com 9 trademarks the following are registered and unregistered trademarks fairch ild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. hisec? disclaimer fairchild semiconductor reserves the right to make chang es without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising ou t of the application or use of any product or circuit described here in; neither does it convey any lice nse under its patent rights, nor the rights of others. these specificatio ns do not expand the terms of fairchi ld?s worldwide terms and conditions, specifically the warranty therei n, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or system s are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instru ctions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. product status definitions definition of terms acex ? across the board. around the world.? activearray? bottomless? build it now? coolfet? crossvolt ? ctl? current transfer logic? dome? e 2 cmos? ecospark ? ensigna? fact quiet series? fact ? fast ? fastr? fps? frfet ? globaloptoisolator? i-lo ? implieddisconnect? intellimax? isoplanar? microcoupler? micropak? microwire? motion-spm? msx? msxpro? ocx? ocxpro? optologic ? optoplanar ? pacman? pdp-spm? pop? power220 ? power247 ? power-spm? programmable active droop? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? scalarpump? smart start? spm ? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tcm? the power franchise ? tinyboost? tinybuck? tinylogic ? tinyopto? tinypower? tinywire? trutranslation? serdes? uhc ? unifet? vcx? wire? datasheet identification product status definition advance information formative or in design this data sheet contains the design s pecifications for product development. specifications may c hange in any manner without notice. preliminary first production this datasheet contai ns preliminary data; supplementary data will be published at a later date. fairchild se miconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet c ontains final specificati ons. fairchild semiconductor reserves the right to make changes at any time without notice to improve design.
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